1. Field of the Invention
The invention relates to a device in the instruction unit of a pipeline processor for instruction interruption, as a function of an event necessitating such an interruption, and for the repetition of instructions after the resolution of the event.
2. Description of the Prior Art
During instruction processing in data processing systems it is not always possible to perform such processing without interruptions since special situations, in the following called events, can occur which necessitate a short interruption to perform the operations caused by such events before continuing the interrupted instruction processing.
Under the present conditions this refers less to sequentially continuing, at the point of interruption, the next instruction than to processing, including a repetition of the last instruction which had detected the event and which had been interrupted before being completed, e.g. with storing an event obtained thereby, because this instruction requires information which can not be made available until the execution of the event.
A typical situation of that kind appears e.g. in data processing systems with a cache provided as a buffer between the main storage and the processing unit. A directory always records the address of the data in the cache. Upon each access of the processor to the cache the directory is interrogated as to whether the data required are stored in the cache so that they can be provided by the cache for the execution of this instruction. If the current address with the necessary data is not located in the directory, the data from the main storage have to be stored in the cache which in turn causes a new registration in the directory. It is only now that instruction processing can be resumed with the repetition of the latest instruction.
This instruction repetition however is only possible if during the interruption the contents of the operation register are stored which contains the instruction, i.e. substantially the operation code and the operand addresses and, if necessary, additional information which can still be comprised in the instruction. Known data processing systems use for that purpose back-up registers whose number depends on the degree of overlapping instruction processes, and which permit the return to the instruction to be repeated, and the re-establishing of the source data.
Apart from this additional amount of components undesirable per se, this kind of instruction repetition involves a significant loss of time since the entire instruction which can comprise one to several clocks (instruction cycles) has to be repeated.